![]() Parallel loading is inhibited when SH/ LD is held high. ![]() Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. The functions of CLK and CLK INH are interchangeable. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial ( Q H) output.Ĭlocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q H) output. Processing Does Not Necessarily Include Testing ![]()
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